library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key_state is
  port(clk, timer, sw2: in std_logic;
       led_show: buffer std_logic_vector(15 downto 0));
end entity;

architecture behave of key_state is
begin

process(clk, timer)
  variable count: integer range 1 to 21;
begin
    if timer'event and timer = '1' then
      if sw2 = '0' or count = 21 then
	    count := 1;
	  end if;
      if count = 1 then
        led_show <= "0000000000000001";
        count := count + 1;
      elsif count = 10 then
        led_show <= "0000000000010000";
        count := count + 1;
      elsif count = 20 then
        led_show <= "0000000000100000";
        count := count + 1;
      else
        led_show <= led_show + 1;
        count := count + 1;
      end if;
    else null;
    end if;
end process;

end behave;